1. Field of Art
The disclosure generally relates to the field of electronic design automation (EDA), and more specifically to reducing leakage power in Integrated Circuit (IC) Designs.
2. Description of the Related Art
Leakage power contributes significantly to the total power of modern ICs. Further, leakage power is a dominant contributor for consuming stand-by power. Many sources of leakage can be traced to the transistors of an IC. For example, gate-oxide tunneling leakage, sub-threshold leakage, punch-through leakage, gain-induce drain leakage and reverse bias leakage are different types of leakage currents found in modern Metal Oxide Field Effect Transistors (MOSFET). Power leakage can be reduced by increasing the threshold voltage or increasing the gate length of the transistors. However, techniques for decreasing power leakage also have the negative consequence of increasing the delay of the transistor.
Additionally, most modern ICs are cell based designs designed from standard cells. The standard cell is a circuit that has been pre-designed and pre-verified as a building block for a design. Examples of standard cells include NAND gates, NOR gates, flip flops, and other logic functions. During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in creating a design for an IC. Copies of the cells (called instances) are then arranged into a floor-plan and then connected together with chip-level metal routing to implement a desired functionality of the IC.
A cell library includes different footprint equivalent variants for various types of cell. For example, a cell library may include three versions of a NOR gate: a low leakage variant, a medium leakage variant, and a high leakage variant. Because of the inverse relationship between leakage and delay, the low leakage variant typically has the highest delay, and the high leakage variant has the lowest delay. Footprint equivalent variants can be interchanged with other variants of the same type of cell without affecting the chip-level routing between cells. Thus, the leakage of an IC design can be reduced without affecting the routing of the design. However, minimizing leakage comes at the expense of decreasing the overall speed of the IC.